Multi-phase clock generation is critical for emerging technologies such as phase array, beam forming, passive mixing, N-path filtering and interleaved data converters. Multi-phase signals can be generated by ring oscillators with either resistive load or inductor/capacitor (LC) based differential gain stages (also known as delay cells). Ring oscillators without an LC tank circuit normally end up with unacceptable phase noise for most wireless applications. It is thus highly desirable to push the phase noise of ring oscillators towards what LC-based oscillators can reach. Recent researches on injection-locked ring oscillators showed promising phase noise performance with the help of off-chip reference sources. N-path filters are also used to enhance the equivalent quality factor of the ring for improved phase noise.
A classical structure of ring oscillator 100 is illustrated in FIG. 1a and FIG. 1b. The differential inverter 102 based ring oscillator comprises multiple differential gain stages 16 with either even 104 or odd 106 number of differential gain stages 16 connected in series. As illustrated in FIG. 2a and FIG. 2b, the differential gain stages 200 could be constructed with (but not limited to) either resistive load 202 or active load 208, which experiences a total amount of phase shifting of 2π to sustain oscillation. The phase noise of ring oscillator 100 is determined by the noise sources from the loading 202 or 208, switching transistors 204 and current source transistors 206.
Properties of poor phase noise in ring oscillators can be relieved by injection locking, which is realized by injecting a periodic signal into the oscillator, leading to improved phase noise performance. Recent researches on injection-locked ring oscillators with PLLs showed promising phase noise performance with the help of off-chip reference sources. With the greatly reduced in-band noise, the loop bandwidth can be widened to help reducing the oscillator's phase noise, enabling inductor-less low jitter frequency synthesis. A prior art injection-locked phase lock loop (IL-PLL) 300 in FIG. 3 is composed of a digitally controlled delay line (DCDL) 302, pulse generator 304, phase and frequency detector/charge pump (PFD/CP) 306, loop filter (LF) 308, divider 314 and voltage controlled oscillator (VCO) 310. The reference signal is shaped into tiny pulse by the pulse generator and then is forwarded into VCO, which leads to the improved in-band phase noise. However, the traditional IL-PLL suffers from high reference spur due to injection process. As illustrated in FIG. 11, reference spurs in IL-PLL mainly comes from two sources: (i) timing mismatches between injection signal and the oscillation waveform and (ii) distortion in the output waveforms induced by injection pulses as illustrated in FIG. 11. Due to non-ideal injection, the output waveform will be distorted and the distortion repeats every reference cycle even if the injection occurs at the waveform's zero-crossing points. This periodic distortion causes reference spur in output spectrum. Pulse width TD sets the lower bound of the reference spur level in conventional IL-PLLs. Moreover, in ring oscillator based IL-PLLs, the distorted waveform in one stage will propagate through other stages, leading to high reference spurs in every output phases. Timing mismatches can be calibrated by using conventional charge pump PLL, as shown in FIG. 3, to track the reference clock as its Nth sub-harmonic, where N is the loop division ratio. However, the distortion in the output waveform from injection pulse cannot be eliminated in prior art injection-locked PLLs.